New Approach for Large Area High Tc Thin Film Technology

The overall objective of this program is to develop a high temperature superconductor (HTS) / low e dielectric / HTS layer structure, where the low e dielectric will have comparable dielectric constant to the layers used in conventional electronic packaging (2.5-5). A high quality, HTS / low e dielectric / HTS layer structure is the enabling technology for many different applications including multi-chip modules, interconnects and high frequency microwaves. HTS interconnects offer significant reductions in rise time caused by RC time constant effects; however, the lowest possible effective dielectric constant is necessary to minimize the signal delay time. Inter-layer shorts and the high dielectric constant of possible materials for epitaxial growth has hindered the building of tri-layers. Tri-layers have been demonstrated on small area (1cm2), but invariably have problems with outgrowths and boulders puncturing the dielectric layer unless a planarization step is used. The focus for the work in Phase I of this program is to investigate laminating superconductor layers with intermediate organic polymers. The self supporting YBCO will be generated using novel etching procedures.