A NOVEL APPROACH FOR DESIGNING BUILT-IN SELF-TESTING VLSI CIRCUITS

THE MAIN OBJECTIVE OF THE OVERALL PROJECT (PHASES I AND II) IS TO RESEARCH, DEVELOP, FABRICATE, AND EVALUATE A BUILT-IN SELF-TESTING MULTIPLIER-ACCUMULATOR FOR SPACECRAFT APPLICATIONS. PHASE I IS A RESEARCH AND DEVELOPMENT EFFORT TO DEMONSTRATE THE FEASIBILITY OF AN INNOVATIVE STRUCTURE THAT COULD OFFER SIGNIFICANT ADVANTAGES IN THE DESIGN OF VERY LARGE SCALE INTEGRATED CIRCUITS CAPABLE OF AUTONOMOUS TESTING. IN ORDER TO EVALUATE THE COST-EFFECTIVENESS OF THE NOVEL BUILT-IN SELF-TESTING STRUCTURE, THE PROPOSED WORK WILL FOCUS ON THE RESEARCH AND DEVELOPMENT OF AN AUTONOMOUS TESTING 16X16 BIT PARALLEL MULTIPLIER. PRESENTLY, MOST AUTONOMOUS TESTING CIRCUITS ARE DESIGNED WITH LINEAR FEEDBACK SHIFT REGISTERS USED EITHER AS GENERATORS OF STIMULI OR AS COMPRESSORS OF RESPONSES. ALTHOUGH THEIR LAYOUT IS COMPACT, THEY ARE INEFFICIENT IN DETECTING CERTAIN TYPES OF FAULTS DUE TO THE PSEUDO-RANDOM NATURE OF THE STIMULI AND THE COMPRESSION OF RESPONSES INTO ALIASING SIGNATURES. THE INNOVATIVE STRUCTURE PROPOSED FOR CONSTRUCTING IMPROVED GENERATORS OR COMPRESSORS IS OBTAINED BY THE ADDITION OF A MICRO PROGRAMMABLE LOGIC ARRAY TO THE LINEAR FEEDBACK SHIFT REGISTER. THE NEW COMBINATION COULD INCREASE SIGNIFICANTLY THE FAULT DETECTION EFFECTIVENESS OF THE STIMULI WITHIN A SHORTER SELF-TEST TIME BECAUSE THE PSEUDO-RANDOM RESISTANT FAULTS COULD BE DETECTED WITH A SHORT SEQUENCE OF DETERMINISTIC STIMULI PRODUCED BY THE LOGIC ARRAY. BECAUSE THE LOGIC ARRAY COULD STORE AND COMPARE MULTIPLE SIGNATURES WITH THE ACTUAL SIGNATURES GENERATED BY THE FEEDBACK SHIFT REGISTER, THE NOVEL COMBINATION COULD AVOID THE ALIASING PROBLEM.