Virtual Memory Redundancy Management for Reliable Multiprocessing

Modified computer-to-memory interface architecture and memory management executive software provide substantial increases in multiprocessor system reliability and throughput. The MIL-STD-1750A computer interface has a local cache memory using 8-word pages. The common main memory has fault tolerant data and address buses and fault tolerant data storage, with a page long word length, and hardware are supported Error Detection and Correction. Transferring a full page in a single memory cycle and the architecture achieves virtually 10 times the single computer throughput with 10 computers. The memory management executive uses the unique EDAC system and data scrubbing to guarantee data integrity. Virtual space assignment and two dimensional memory IC sparing are managed in real time to achieve, in a minimum cost way, a Ps of nearly 1 for any length mission. For a 10 year mission Ps>0.99 approximately 40% overhead is needed. Demonstration will be achieved by stimulating the satellite payload and stationkeeping program examples using a modified version of the CDC 444RRR Software Development System hardware model.