Automated Parallel Algorithm VHDL Software Tool For Use in Generating Custom FPGA Coprocessors

This Small Business Innovation Research Phase I project addresses the problem of automatically generating optimal parallel custom hardware implementations from high level algorithm descriptions. The proposed software tool generates a minimum- execution-time dependence graph associated with the parallel algorithm implementa- tions and a translator converts this to a VDHL description. The tool will be applied to the problem of designing FPGA reconfigurable computer architectures for use as a "coprocessor" in embedded DoD applications. Our proposed software tool can be systematically applied, thus doesn't depend on knowledge of appropriate heuristics to formulate the problem and make tradeoffs. In addition, it is particularly well suited to DoD missions where non-optimal solutions exact an extremely high price in terms of system parameters such as power, volume, speed, and weight.