HIGH EFFICIENCY ADA COMPILER

MOST OF THE CURRENT ADA COMPILER IMPLEMENTATIONS DO NOT ALLOW THE DEVELOPMENT OF EMBEDDED SYSTEMS SOFTWARE DUE TO A VERY LARGE OVERHEAD IN TERMS OF OPERATING SPEED AND MEMORY REQUIREMENTS. THE PHASE I PROPOSAL WILL COME UP WITH THE DESIGN OF A HIGH EFFICIENCY ADA COMPILER THAT WOULD EXECUTE WITH MINIMAL PERFORMANCE DEGRADATION AND MEMORY REQUIREMENTS, IN THE RANGE OF 16K TO 64K BYTES FOR THE TOTAL SYSTEM, APPLICATION AND OVERHEAD. THE FOLLOWING AREAS ARE OF MAJOR CONCERN WHEN DESIGNING A HIGH EFFICIENCY ADA COMPILER A) DESIGN OF THE ADA RUNTIME SYSTE, B) OPTIMIZATIONS AND CODE GENERATION ALGORITHMS, C) SIZE OF THE ADA RUNTIME SYSTEM AND SELECTIVE LINKING OF THE OBJECT CODE. TECHNIQUES FOR IMPLEMENTING ADA FEATURES SUCH AS TASKING, INTERRUPTS, EXCEPTIONS, MEMORY MANAGEMENT, INPUT/OUTPUT ETC. WILL BE EXPLORED SO AS TO MINIMIZE EXECUTION TIME AND MEMORY USAGE. NEW GLOBAL OPTIMIZATION TECHNIQUES AND CODE GENERATION ALGORITHMS WILL BE RESEARCHED. THESE ALGORITHMS GREATLY IMPROVE THE POTENTIAL FOR PRODUCING HIGH EFFICIENCY ADA COMPILERS. EXPERIMENTS WILL BE PERFORMED TO DETERMINE THE FEASIBILITY OF THE DIFFERENT TECHNIQUES USING AN ADA COMPILER SYSTEM TARGETED TO A BARE MACHINE.