NON-VOLATILE VHSIC-DENSITY NEURAL NETWORK CHIP WITH VARIABLE WAFER DICING

RECENT DEVELOPMENTS IN NEURAL NETWORKS HAVE SHOWN THAT THEIR EFFECTIVE APPLICATION IS DEPENDENT UPON THE ABILITY TO PRODUCE VERY LARGE NETWORKS WITH HIGH CONNECTIVITY. AS A RESULT, EXTREMELY POWERFUL NEURAL NETWORKS ARE REQUIRED TO SOLVE MANY VITAL DOD PROBLEMS IN REAL-TIME. THESE NETWORKS MUST HAVE A MODULAR STRUCTURE SO THAT INCREASINGLY POWERFUL NETWORKS CAN BE BUILT EASILY. WE PROPOSE TO CHOOSE A REPRESENTATIVE SET OF NEURAL NETWORK ARCHITECTURES WITH APPROPRIATE LEARNING RULES AND DEFINE A SINGLE, VHSIC-DENSITY CHIP ARCHITECTURE THAT CAN SUPPORT ALL OF THEM. WE WILL DEVELOP A COMPUTER MODEL OF THE CHIP AND SHOW THAT IT SUPPORTS THESE NEURAL NETWORK ARCHITECTURES. TO HANDLE MANUFACTURING DEFECTS THAT ARE INEVITABLE IN THE PRODUCTION OF COMPLEX CHIPS, WE FURTHER PROPOSE TO DEFINE A CHIP ARCHITECTURE THAT ENABLES DIFFERENT NUMBERS OF UNSAWN DICE TO BE MECHANICALLY AND ELECTRICALLY CONNECTED TOGETHER. THIS WILL PROVIDE MANY OF THE PRESUMED ADVANTAGES OF WAFER SCALE INTEGRATION, BUT RESULT IN LARGE NUMBERS OF USABLE DEVICES. TO STORE THE WEIGHT MATRICES THAT ARE BING UPDATED BY LEARNING ALGORITHMS DURING OPERATION OF THE SYSTEM, WE FURTHER PROPOSE TO INVESTIGATE THE APPLICATION OF FERROELECTRIC MEMORY TECHNOLOGY.