Design Tools for Integrated Asynchronous Electronic Circuits

"As progress in deep submicron technology exacerbates issues of clockdistribution, power consumption, control and estimation of delays, and designcomplexity, asynchronous techniques are becoming more and more attractive.The single most severe impediment to the adoption of asynchronous technologyby industry is the lack of an industrial-strength-level suite of CAD tools forasynchronous VLSI design.The design of an asynchronous MIPS R3000 microprocessor in 1998 and thecurrent design of an asynchronous 8051 microprocessor (both developed atCaltech in the proposer's laboratory) have demonstrated that asynchronoustechniques can indeed produce circuits with both high throughput and low powerconsumption, without sacrificing the robustness and reliability offered by a{\it quasi delay-insensitive approach\/}, i.e. without introducing delayassumptions. Both chips were designed using a top-down methodology thatincludes synthesis at both logical and physical levels, simulation atdifferent levels of synthesis and in mixed-level mode, and performanceanalysis and optimization. The prototype suite of tools was called CAST. Allchips designed at Caltech using CAST were found entirely correct on firstsilicon.The objective of this proposal is to demonstrate the feasibility of a suite ofindustrial CAD tools for asynchronous, quasi delay-insensitive, VLSI circuits,based on CAST and the Caltech methodology. It is expected that the availability of CAD tools