Modeling of CMP and Photolithographic Pattern Printing Equipment Variations and the Impact on Circuit Performance

Chemical-mechanical polishing (CMP) is an emerging process technology that planarizes the dielectric in multi-layer interconnect structures during integrated circuit (IC) fabrication. CMP is an important technology to support multilayer interconnect. Since the results of CMP is dependent on the topography of the chip, systematic spatial variations due to layout pattern dependencies are, today, unavoidable. Since CMP variation dominate interconnect dielectric variation, these systematic spatial dependence can have a significant impact on speed variations and potential race conditions. By leveraging from existing research at MIT, as well as PDF's background in TCAD frameworks and statistical modeling, we propose to determine the requirements software and engineering methods which couple CMP equipment, chip and feature level simulation. The eventual goal is to provide an environment for predicting the variations in interconnect capacitance as a function of CMP equipment settings. Such a system would help defray the costs of applying CMP to low volume products. This project will have widespread impact on CMP tool and sensor improvement; process design, optimization and control; and integrated circuit design for manufacturability. Development of software which makes CMP techniques more affordable and reliable is of great interest to most commercial and military manufacturers. Moreover, only physically-based simulation will render CMP viable for low-volume applications such as those common in the defense community.