A FRAMEWORK FOR THE DESIGN OF HIGH SPEED INTERCONNECTIONS

INTERCONNECTIONS BETWEEN LOGIC BLOCKS PLAY AN INCREASINGLY IMPORTANT ROLE IN TODAY'S HIGH PERFORMANCE MICROCIRCUIT DESIGNS. PERFORMANCE VIOLATIONS DUE TO INTERCONNECT EFFECTS SUCH AS PROPAGATION DELAYS, DISPERSION, ATTENUATION, RINGING, REFLECTION AND CROSSTALK MUST BE DETECTED BEFORE A DESIGN IS COMMITTED TO PRODUCTION. THE RECENTLY DEVELOPED ASYMPTOTIC WAVEFORM EVALUATION (AWE) TECHNIQUE PROMISES TO DRASTICALLY REDUCE THE COMPLEXITY OF THE EXTRACTION AND SIMULATION PROBLEMS, THE CRUCIAL VERIFICATION STEPS IN INTERCONNECT DESIGN. THE INCREASED EFFICIENCY OF THE VERIFICATION TECHNIQUES WILL ALLOW THE INCORPORATION OF THE VERIFICATION TECHNIQUE WITHIN THE DESIGN PHASE TO ENSURE THAT SYSTEM SPECIFICATIONS ARE MET. A DESIGN SYSTEM INCORPORATING THE VERIFICATION AND LAYOUT TOOLS AND INTERACTING WITH AN INTERCONNECT DATABASE, AS WELL AS LIBRARIES OF NONLINEAR DRIVER AND LOAD MODELS AND INDUSTRY STANDARD LAY-OUT DATABASES IS PROPOSED FOR AN AUTOMATIC AND COMPREHENSIVE SOLUTION TO THE INTERCONNECT DESIGN PROBLEM. THIS AUTOMATION WILL SIGNIFICANTLY REDUCE DESIGN TIME AND THUS TIME TO MARKET OF HIGH PERFORMANCE SYSTEMS. ANTICIPATED BENEFITS: AN AUTOMATED DESIGN SYSTEM FOR HIGH SPEED INTERCONNECT WILL SIGNIFICANTLY REDUCE THE DESIGN TIME OF HIGH PERFORMANCE ELECTRONIC CIRCUITS. THE REDUCTION IN DESIGN TIME CAN BE TRANSLATED INTO IMPROVED TIME TO MARKET.