SBIR/STTR Research Award
Tools for Reliable and Manufacturable VLSI Microcircuits
Award amount
$59,945Program and phase
SBIR · Phase IAward year
1994Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- Dqdt
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
The goal of this proposal is to assess the feasibility of, and implement an initial demonstration of, a VHDL-based tool where the reliability concerns of a VLSI microcircuit can be considered during the high-level specification phase of the design. Great strides are being made in tailoring design tools to optimize a microcircuit in terms of speed, area, and power consumption by allowing the designer to judiciously trade off these conflicting characteristics against one another. DQDT has completed a phase I feasibility study on parameterized VHDL-based generators that create a gate-level description from high-level specifications. This proof of concept allows the designer to explore the design space with finer granularity than existing commercial tools. We propose to enhance an existing, parameterized VHDL-based DSP function generator by including reliability-related input information to ensure that the designed microcircuit achieves the required reliability. The feasibility of adapting this existing generator to prevent a host of potential reliability problems will be explored. Electromigration and hot-carrier degradation will be incorporated into the existing generator. Other effects could be incorporated during follow-ons to this task. By adapting an existing VHDL-based tool, the risk can be substantially reduced.
Technology keywords
Not reported