HIGH PERFORMANCE CMOS DIGITAL INTEGRATED CIRCUITS USING SI1-XGEX PMOSFETS

WE PROPOSE TO DEVELOP ULTRA FAST LSI/VLSI CMOS CIRCUITS USING SI1-XGEX CHANNEL PMOS AND SI CHANNEL NMOS DEVICES INTEGRATED ON THE SAME CHIP SUITABLE FOR STRATEGIC DEFENSE SYSTEMS. SINCE THE MOBILITY OF THE PMOS SIGE CHANNEL DEVICES ATLEAST BY 50% THE CMOS CIRCUITS WILL HAVE HIGHER PACKING DENSITY (DUE TO SMALLER PMOS CELLS) AND HIGHER SPEED. WE WILL IDENTIFY A SUITABLE PROCESS COMPATIBLE WITH EXISTING CMOS TECHNOLOGY WITH MINIMAL MODIFICATIONS. THE GATE DIELECTRIC (SILICON DIOXIDE) LAYER WILL BE THERMALLY GROWN USING A SILICON CAP LAYER GROWN ON THIS SIGE ACTING AS THE CHANNEL LAYER FOR THE PMOS DEVICES. THE CHANNEL SIGE LAYER WILL BE UNDOPED AND THE VALENCE BAND DISCONTINUITY WILL RESULT IN A MODULATION DOPING CONTRIBUTING TO FREE HOLES CONFINED IN THE CHANNEL. WE WILL OPTIMIZE THE CHANNEL LAYER, CAP LAYER AND BUFFER LAYER THICKNESSES ALONG WITH THE DOPING CONCENTRATIONS FOR ACCEPTABLE PMOS THRESHOLD VOLTAGE. IN PHASE I, WE WILL DELINEATE THE FABRICATION PROCESS AND DESIGN THE DEVICE STRUCTURE. WE WILL ALSO DESIGN SEVERAL BASIC CELLS SUING THIS EXCITING MIXED CMOS TECHNOLOGY FOR VARIETY OF DIGITAL AND SIGNAL PROCESSING CIRCUITS AND OPTIMIZE THE DESIGN USING PROCESS, DEVICE AND CIRCUIT SIMULATIONS. ANTICIPATED BENEFITS: HIGH SPEED DATA PROCESSORS, HIGH DENSITY CMOS DIGITAL CIRCUITS AND FAST VLSI SYSTEMS.