SBIR/STTR Research Award

AN ADA-BASED REAL-TIME REDUCED INSTRUCTION SET COMPUTER (RISC) MICROPROCESSOR

Award identifier 0810af410eee5d7dc3141230ab9f8c2844358bbb93a27597c3b98f58e8f12f35Awarding agency National Science Foundation

Award amount

$50,000

Program and phase

SBIR · Phase I

Award year

1989

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Akm Associates, Inc.
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

AN IMPORTANT CLASS OF COMPUTER APPLICATIONS HAS THUS FAR EVADED EXTENSIVE ARCHITECTURAL ANALYSIS AND DESIGN--REAL-TIME SYSTEMS. IN PARTICULAR, REAL-TIME MICROPROCESSOR ARCHITECTURES HAVE NOT BEEN DEVELOPED AS PARTOF LARGER, INTEGRATED SYSTEMS BASED ON HIGHER LEVEL PROGRAMMING LANGUAGES. REDUCED INSTRUCTION SET COMPUTER (RISC) ARCHITECTURAL TECHNOLOGY HAS DEMONSTRATED ITS EFFECTIVENESS AS A MEANS OF CONSTRUCTING COST-EFFECTIVE HIGH-PERFORMANCE PROCESSORS, AND HAS BEEN SUCCESSFULLY SPECIALIZED TO SUPPORT SPECIFIC PROGRAMMING LANGUAGES. THE ADA PROGRAMMING LANGUAGE HAS BEEN DESIGNED TO SERVE REAL-TIME, EMBEDDED APPLICATIONS, AND HAS BEEN IMPLEMENTED ON A NUMBER OF PROCESSORS. IN THIS PHASE I EFFORT, THE RESEARCHERS PROPOSE TO EXAMINE CURRENT RISC MICROPROCESSORS AND MEASURE EXISTING ADA IMPLEMENTATIONS, WITH THE INTERMEDIATE (I.E., PHASE II) GOAL OF DETERMINING WHAT HARDWARE SUPPORT, IF ANY, COULD SIGNIFICANTLY IMPROVE ADA REAL-TIME PERFORMANCE AND WITH THE ULTIMATE (I.E. PHASE III)GOAL OF DEVELOPING A RISC MICROPROCESSOR FOR ADA, IF FEASIBLE.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

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