APPLICATION OF VLSI TO VECTOR ACCUMULATORS AND INTEGRATING TIME TO DIGITAL CONVERTER

DESIGN, SIMULATION, FABRICATION, AND EVALUATION OF A PROTOTYPE VERY LARGE SCALE INTEGRATION (VLSI) DATA ACQUISITION SUBSYSTEM IS PROPOSED. AVAILABLE STATE-OF-THE-ART ONE MICRON CMOS TECHNOLOGY MAY ALLOW INCORPORATION OF MORE THAN 128 CHANNELS OF 24-BIT 300 MHZ COUNTERS INTO A SINGLE INTEGRATED CIRCUIT. A PROTOTYPE SYSTEM OF SIMPLE REPEATED CELLS OF COUNTERS, CONTROL AND I/O BUFFERS HAS BEEN DESIGNED FOR THE EVALUATION OF THE FEASIBILITY OF CONSTRUCTING INTEGRATED NUCLEAR DATA SUBSYSTEMS AND PRE-PROCESSORS. THE PROTOTYPE DEVICE HAS VERSATILE CONTROL CIRCUITRY ALLOWING OPERATION AS A MULTICHANNEL SCALER (MCS), A ZERO DEAD-TIME INTEGRATING TIME-TO-DIGITAL CONVERTER (ITDC), OR A VECTOR ACCUMULATOR (VA). CONSTRUCTION OF SPECIFIC DATA ACQUISITION SYSTEMS IS INTENDED IN FOLLOW ON WORK AND IS DISCUSSED.