GAAS WAFER TESTING FOR RADIATION-INDUCED TRANSIENT UPSET

THE DEVELOPMENT OF A WAFER-LEVEL TESTING TECHNIQUE FOR MULTIGIGAHERTZ GAAS DIGITAL INTEGRATED CIRCUITS TO CHARACTERIZE THE TRANSIENT-RADIATION-INDUCED UPSET LEVEL IS PROPOSED. THIS CONCEPT WILL ALLOW THE OPTIMIZATION OF THE UPSET LEVEL IN HIGH PIN-OUT DENSITY CIRCUITS USING AN ON-SITE, QUICK TURNAROUND PROCEDURE FOR TECHNOLOGY DEVELOPMENT AS WELL AS CIRCUIT SCREENING. THIS NONDESTRUCTIVE TECHNIQUE CAN BE APPLIED TO ESTABLISH THE ULTIMATE UPSET LEVEL WITHOUT EXPENSIVE OFF-SITE QUALIFICATION TESTING. THE PHASE I FEASIBILITY STUDY WILL INCLUDE THE THE IMPLEMENTATION OF SUITABLE SUBBANDGAP LASER SOURCE FOR WAFER-LEVEL SIMULATION, THE DEVELOPMENT OF A SUITABLE DATA BASE TO ESTABLISH CORRELATION BETWEEN LASER AND CONVENTIONAL LINAC SIMULATION FOR VARIOUS TEST DEVICES AND CIRCUITS; AND DEMONSTRATION OF THE APPLICABILITY OF THE LASER SIMULATION TECHNIQUE TO STATE-OF-THE-ART GAAS CIRCUITS BY EXTENDING THE EXPERIMENTAL DATA BASE WITH PHOTORESPONSE SIMULATION.