SBIR/STTR Research Award

AN OPTOELECTRONIC THYRISTOR BASED ANALOG TO DIGITAL CONVERTER

Award identifier 32047ae12df4b16b361e72944dd9a04b371db34b4afaafdab6521bf0521c322aAwarding agency Department of Defense · Air Force

Award amount

$98,225

Program and phase

SBIR · Phase I

Award year

1998

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Intelligent Automation, Inc.
Proposal award date
Not reported
Contract end date
Not reported
UEI
C3QJD7VXG167
Solicitation number
Not reported
Topic code
Not reported

Research abstract

A unique thyristor laser implements a high performance Analog to Digital Converter (ADC) in a monolithic FET GaAs integrated circuit. In the curent high speed FLASH ADC, the comparator circuit performs in the sampling on the input analog signal by comparing it to a voltage reference tree and the outputs are converted to binary form via a decimal to binary (DTB) algorithm stored in a ROM. To achieve substantial increases in ADC accuracy, speed and circuit density, we propose a comparator based on an optoelectronic thyristor which is electrically switched and provides laser ouput as a VCSEL in the on state. We introduce an elegant new architecture to implement the ADC function which merges the roles of the quantization, the DTB conversion and the O/E conversion within a simple integrated circuit. One thyristor and one Differential amplifier are required per binary digit. This new approach reduces the number of devices required for a 12 bit ADC from 100,000 to 70 and reduces the ADC delay from 50ns to 0.5ns. The power is correspondingly reduced and the output is a digital optical signal in serial or parallel format. The voltage resolution is in the 5mV range limited only by the dark current noise in the switch. This approach provides a quantum leap in an N bit ADC speed because the output is obtained optically in the time that it takes the analog signal to ripple through N stages at 40ps/stage. This technique promises to revolutionize the art of ADC and to provide the basis for very high speed image transfer for the future all digital network. In addition to this novel conversion we also provide the integrated technology to realize the VCSEL thyristor, the FET amplifier and CCD sensor simultaneously.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

1,182 SBIR/STTR records share this UEI (1987–2021). Reported award amounts total $369,972,257. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Transportation, Department of Health and Human Services, National Science Foundation, Department of Homeland Security

Agency intelligence

Department of Defense

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