SBIR Phase I: Virtual Flow Pipelining Based Radio Communication Chip Architecture

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5). This SBIR Phase I research proposal will develop architectural solutions for programmable radio devices. The emergence of multiple radio access technologies and their continued evolutionary development drive a need to support them in a programmable manner. The objective is to enable flexibility for future evolution while ensuring processing of high data bandwidths. Current practices are based on the Software Defined Radio (SDR) approach. This approach lacks performance, is difficult to program and silicon-on-chip (SoC) devices are complex. The Virtual Flow Pipelining architecture proposed here enables programmable SoC devices with low hardware complexity, simple programming model, and high performance. These characteristics are achieved using atomic architectural support for the function synchronization, scheduling, sequencing and communication with performance guarantees. The benefits of the programmable platform are longer lifetime of devices, faster time to market, and universal reach. It will simplify prototyping effort, and accelerate product and technology adoption. The market opportunities for commercialization are wireless protocol IP cores with semiconductor companies such as Intel, Broadcom, Qualcomm as target customers.