Vertical Interconnects for 3D CMOS Imager

NanoSciences proposes to develop a vertical interconnect structure base on a novel high rate through wafer micromachining process for application to a novel massively parallel high-performance smart 3D CMOS imaging technology under development at JPL. The smart imager will exhibit ultra high contrast handling capacity and high speed readout for defense and reconnaissance applications with special emphasis on anti-blinding, fast tracking, and high speed object identification and acquisition. Large format 2D focal plane arrays have been built in both CCD and CMOS technology although imaging performance continues to improve, it comes at the cost of reduced dynamic range, reduced speed, and increased power dissipation. Reduced speed is of particular concern for space based tracking, reconnaissance and robotic applications, that require faster than real-time imaging for high-speed closed loop control systems. The above-mentioned problems can be solved by processing data closer to the imager sense elements employing vertically interconnected structures. Vertical stacking solves the problem of interconnectivity leading to the development of smart focal planes without sacrificing imaging performance. The development of a reliable vertical interconnection presents a significant technical challenge, if successful, it will revolutionize new imager architectures and circuits, enabling smart imager development.