STTR Phase II: Blended Clocked and Clockless Integrated Circuit Systems

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5). This Small Business Technology Transfer (STTR) Phase II research project will develop and apply a principled design methodology to confront the serious problems associated with deep sub-micron, system-on-chip, integrated-circuit designs. The project will develop design services for companies wishing to market complex, proprietary, low-power integrated circuits through the development of a unique design tool, one which will apply a mathematically sound approach to the production of large, hazard-free, network-on-chip products. The goal for this tool is to reduce traditional design cycles by eliminating most of the global verification effort while improving the robustness of the design. New results in predicting the behavior of deep submicron arbiter circuits are essential to this work and will also be reported. The broader impacts of this research are to reduce design costs, time-to-market and power consumption. More broadly this can: 1) significantly increase the productivity of integrated-circuit design engineers, 2) reduce power consumption of electronic control, communication and computational systems and 3) increase our competitiveness against off-shore system-on-chip designers particularly with respect to low volume products. Thus, successful completion of this project is important to the future of the national electronics marketplace because, without a major reduction in the time spent on global verification, the benefits of higher levels of integration, including reductions in time-to-market, conservation of power and increases in reliability, will not be available to many important electronics market sectors.