IN-ARRAY DIGITAL BEAM FORMING ARCHITECTURE

IT IS PROPOSED TO DEVELOP AND EVALUATE AN ARCHITECTURE FOR A MULTIELEMENT RADAR RECEIVING ARRAY WHICH PERFORMS DIGITAL BEAM FORMING (DBF) WITHIN THE RECEIVING ARRAY ITSELF, USING EACH ELEMENT AS A NODE OF A SYSTOLIC-LIKE ARRAY PROCESSOR. THE PROCESSOR ASSOCIATED WITH EACH ELEMENT OF THE ARRAY WILL PRODUCE A DIFFERENT SPATIAL BEAM. THIS DISTRIBUTED ARRAY PROCESSING CAPABILITY CAN BE REALIZED BY ADDING A SMALL AMOUNT OF DIGITAL CIRCUITRY TO EACH ELEMENT AND BY PROVIDING ELEMENT-TO-ELEMENT INTERCONNECTION IN A NOVEL AND EFFICIENT MANNER WHICH MINIMIZED INTERCONNECTION WIRING. THIS APPROACH CONTRASTS WITH CONVENTIONAL DBF ARCHITECTURES WHICH PERFORM ONLY QUANTIZATION AT EACH ELEMENT. THE QUANTIZED DATA FROM EACH ELEMENT IS PASSED TO A CENTRAL PROCESSOR FOR WEIGHTING AND SUMMING. THE HIGH AGGREGATE DATA RATE OFTEN REQUIRES A LARGE NUMBER OF PARALLEL DATA LINES. THE PROPOSED APPROACH PERMITS THE TRANSMITTED DATA TO BE REDUCED TO ONLY THOSE SPATIAL BEAMS OF CURRENT INTEREST, THEREBY REDUCING THE REQUIRED DATA RATE. THE PROPOSED DEVELOPMENT AND EVALUATION EFFORT WILL INCLUDE ANALYSIS AND ASSESSMENT OF THIS DBF APPROACH FOR SURVEILLANCE AND MULTI-TARGET TRACKING APPLICATIONS, AS WELL AS REFINEMENT OF THE BASIC ARCHITECTURAL CONCEPT TO ACCOMMODATE THE BROADEST POSSIBLE RANGE OF APPLICATION SCENARIOS. SUCCESSFUL DEMONSTRATION OF BASIC SYSTEM FEASIBILITY WILL LEAD TO THE DESIGN AND EVENTUAL FABRICATION OF APPROPRIATE CUSTOM VLSI PROCESSOR ELEMENTS.