SBIR Phase I: Magnetoresistive Device for THz-uW Computing (EOHW7)

This Small Business Innovation Research (SBIR) Phase I project focuses on further development of magneticmetal transistor that will lead to THz-uW processors and nonvolatile universal memories within 12 month. This transistor, called MDEV (Magnetoresistive Device), was invented at the company working on this award. The transistor employs magnetic spin to determine transistor characteristics. Because atoms and power density do not scale, CMOS scaling is leading to unsustainable thermal levels, performance limits, and escalating cost. Materials innovation such as strained Si, high-K, double gate, FinFET, CNT (Carbon Nano-Tube), and spin-electronics are either still confined to laboratories or too expensive to be widely available. Because MDEV can be built using only standard CMOS metallization equipment on blank silicon wafers, it can be commercialized quickly and cheaply. The first MDEV-based product is a universal memory named M3 (Metal Magnetic Memory). M3 is expected to be Nonvolatile, faster than SRAM, and comes in high density. Because it has unlimited write endurance, M3 is suitable for code and data applications. The research objective of this project is to: i) Optimize and characterize MDEV structures. ii) Create MDEV based memory (M3) prototypes. iii) Evaluate these chips in memory performance (e.g. write/read time, write/read power), environmental endurance (e.g. elevated temperature operations) and process yields. The current wave of semiconductor growth is driven by mass-market electronics in consumer and wireless applications. If successful MDEV based memories and processors will allow designers to improve performance (THz) and reduce power consumption (uW) without cost increases. MDEV memory (M3) is expected to be price competitive with SRAM, NOR and EEPROM today, and is targeted initially as direct replacement for SRAM, EEPROM and NOR Flash, a combined market size of $12B. The long term goal of this effort is to enable designers to simplify their designs in reducing multiple memory technologies (e.g. SRAM and NOR Flash for data and code applications respectively) to one universal memory (M3). MDEV will also be used to build very high performance adaptive processors that combine FGPA's flexibility and low NRE with ASIC's high performance, low power and low unit cost.