Radiation Hard, Stacked LADAR Circuits

To engender future developments in space-based ladar systems, innovative approaches to realizing high-density, radiation-hard readout integration circuits (ROIC) are required. The object of this proposed effort is to support space-based ladar sensingsystems by developing a radiation hard, high-performance, ladar ROIC based on wafer-stacked, rad-hard, SOI CMOS integrated circuits that achieve high-density, mixed-signal processing circuitry in a reduced footprint such as required of interceptor LADARreceiver circuits with superior range resolution, range accuracy, dynamic range.The proposed stacked readout structure consists of two layers of silicon-on-insulator (SOI) semiconductor circuits that are bonded together and interconnected. The structure of SOI, which consists of a thin epitaxial layer on top of a buried oxide andhandle substrate, makes it ideally suited for incorporation into stacked and interconnected structures. As the SOI stacked layers are less than 1-mm thick, alignment and via interconnection is straightforward. In addition to low capacitance, radiationhardness, and high transistor density, the isolation afforded by SOI materials allows high speed, mixed signal circuits to be implemented in a single circuit.In Phase I, we will develop the stacked circuit architecture, design and simulate the ROIC circuitry, detail the manufacturing processes, develop LADAR seeker performance estimates, and deliver a comprehensive Phase II development plan. The proposed innovation is an enabling technology that will engender the development of high performance LADAR systems for a wide range of military, autonomous navigation, electronic aviation landing systems, three-dimensional modeling, land surveying,atmospheric measurements, space docking systems, automotive safety systems, among others.