Complentary 2-D MESFET for Low Power Electronics

The primary objectives of this Phase I effort are to assess the feasibility of developing a p-channel 2-D MESFET and to determine the extent of the significant reduction in power consumption of integrated circuits which may be achieved by utilizing a complementary 2-D MESFET technology. The new FET technology promises to eliminate the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum power consumption of VLSI circuits. By eliminating the NCE, we may scale the device size dramatically and reduce the power consumption by an order of magnitude. Specifically, this project will assess the feasibility to fabricate p-channel 2-D MESFET devices, develop p-channel device models and incorporate these models into an advanced SPICE package (AIM-SPICE), simulate complementary 2-D MESFET circuits, and compare the predicted performance with the existing complementary FET technologies. We will also analyze the primary factors limiting the noise margins at low power supplies, establish the minimum required bias voltage for reliable operation, and analyze the factors determining the threshold voltage changes from device to device as well as other factors which may limit the yield and integration scale.