THREE-DIMENSIONAL WAFER-SCALE INTERCONNECT AND PACKAGING USING PHOTOSENSITIVE GLASS-CERAMIC SUBSTRATES

THE PURPOSE OF THIS PROJECT IS TO DEVELOP AND DEMONSTRATE AN INNOVATIVE NEW APPROACH TO MULTI-CHIP, WAFER-SCALE INTERCONNECT AND PACKAGING USING NEW PHOTOIMAGEABLE GLASS-CERAMIC AND POLYIMIDE MATERIALS THAT CAN BE PROCESSED WITH CONVENTIONAL PHOTOLITHOGRAPHY TECHNIQUES. THE SUPERIOR PROPERTIES OF THESE MATERIALS INCLUDE A CAPABILITY FOR PRECISION FABRICATION OF COMPLEX THREE-DIMENSIONAL STRUCTURES FOR PLANAR CHIP BONDING, DIRECT HEAT REMOVAL, WAFER STACKING FEEDTHROUGH VIAS AND MATCHED IMPEDANCE TRANSMISSION LINES. THE PHASE I EFFORT IS FOR A DEMONSTRATION OF THE NEW PACKAGING APPROACH BY FABRICATING AN IBM PC CLONE CPU/RAM ON A SINGLE ONE-INCH SQUARE SUBSTRATE WITH RECESSED CHIP CAVITIES. THE PHASE II EFFORT WILL INCLUDE DEMONSTRATIONS OF THERMAL AND WAFER STACKING VIAS AS WELL AS CONTROLLED IMPEDANCE LINES.