Single Event Latchup Mitigation in Commercial Microelectronics

Nanosat technology will require commercial-off-the-shelf (COTS) integrated circuits (ICs) to meet the performance requirements. Single event latchup (SEL) triggered by energetic ions in the space environment is a reliability concern. Thinning the Si substrate material below the active region in the CMOS structure raises the threshold linear energy transfer (LET) threshold for energetic ions to trigger SEL because the thinner substrate region produces less charge when the ion penetrates. With a higher LET threshold, there are fewer ions capable of triggering SEL, rendering the IC more radiation-tolerant with respect to SEL. The innovation of this approach is that substrate thinning will be applied to unhardened ICs which are purchased from commercial vendors and post-processed (thinned and possibly ion implanted) and packaged as a radiation-tolerant product. This will enable use of a large class of high-performance ICs that would not otherwise be acceptable for use in the space radiation environment. The significance of this innovation is that it will reduce susceptibility of COTS microelectronics to SEL and enable their use in future NASA missions. In Phase I we will assess the feasibility of the approach and in Phase II we will demonstrate prototypes.