SBIR/STTR Research Award

Virtual Thermal Packaging and Testing of MCMs

Award identifier f0ca14b0d64f1d17a4d12ffd8614a3655c6194bcf2ff44dfb92631bc35e919f5Awarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$366,065

Program and phase

SBIR · Phase II

Award year

1996

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
CFD Research Corporation
Proposal award date
Not reported
Contract end date
Not reported
UEI
V3KCP1HNFM33
Solicitation number
Not reported
Topic code
Not reported

Research abstract

In recent years, major advances have been made in nearly all areas of microelectronics development, including silicon technology, software development, and chip architecture. The one key area that has been more-or-less neglected however is packaging. The technology of packaging minature electronics such that they do not overheat is now the limiting factor in miniaturization. Experimental evaluation of the thermal management of Miniature Multi-Chip Modules (MCMs) and their board/system assemblies can be expensive and time consuming. A novel Virtual Prototyping Environment (VPE) for multi-scale thermal packaging and testing of MCMs and their assemblies is proposed. It involves CAD technology, Virtual Parts Repository, grid generation, heat transfer and cooling media fluid mechanics solver, visualization tools, a thermal stresses module and Property Data Bank. It will allow rapid "virtual assembly" of chips, substrates, interconnects, and encapsulation components of MCM's and their thermal simulation, including thermal cycling and thermal stresses. An electronic component supplier, with the proposed VPE, could deliver a "virtual chip: for system virtual integration before the hardware is shipped. In Phase I, the flow and heat transfer solver will be adapted and demonstrated for thermal packaging and thermal cycling testing of MCMs. A Virtual Parts Repository will be designed. Results of the Phase I effort and the VPE concept will be presented to SEMATECH, the U.S. electronic industry and academic Microelectronics Packaging Centers. Potential teaming/co-funding arrangements will be explored for Phases II and III. ANTICIPATED BENEFITS: The developed computational environment will help in design and thermal cycling testing of MCM's and MCM assemblies. The proposed Virtual parts Repository/Assembly will allow component suppliers to produce "virtual chips" before hardware is delivered for real assembly. The technology will be actively promoted in U.S. electronics, computer, automotive, telecommunication, and defense markets.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

947 SBIR/STTR records share this UEI (1987–2026). Reported award amounts total $350,893,199. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Health and Human Services, National Science Foundation, Department of Commerce, Department of Energy

Agency intelligence

Department of Defense

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