A low-power and high performance stereo vision processor for robotic navigation

This Small Business Innovative Research Phase I project proposes to develop a novel high performance hardware implementation of the stereo vision algorithm developed at JPL by Larry Matthies and co-workers in the Machine Vision Group. While there have been a number of reported hardware implementation reported to-date, our implementation will be the first such implementation to achieve all four design objectives, these being: real-time capability (1 to 30 Hz frame rate); high-resolution images (up to 640x480 raw stereo images pairs); ultra-low power consumption (300 mW or less); design compactness (single chip implementation)Our architecture is based on a novel hardware design that is highly parallel, fully pipelined, computationally efficient, and can be implemented on radiation hardened field programmable gate arrays (FPGA) or ASICs, and is particularly well suited for robust, real-time and high-resolution depth-of-field computations as required by the next generation of on-board robotic navigation systems for planetary exploration.