DEVELOPMENT OF HARDWARE FOR PARALLEL ASYNCHRONOUS FOCAL PLANE IMAGE PROCESSING

RESEARCH IS PROPOSED ON SILICON DEVICES WHICH PROVIDE A NATURAL BASIS FOR PARALLEL ASYNCHRONOUS FOCAL PLANE IMAGE PREPROCESSING. THE SIMPLICITY AND NOVEL PROPERTIES OF THE DEVICES WOULD PERMIT AN INDEPENDENT ANALOG PROCESSING CHANNEL TO BE DEDICATED TO EVERY PIXEL. A LAMINAR ARCHITECTURE BUILT FROM ARRAYS OF THE DEVICES WOULD FORM A TWO-DIMENSIONAL ARRAY PROCESSOR WITH A 2-D ARRAY OF INPUTS LOCATED DIRECTLY BEHIND THE FOCAL PLANE DETECTOR ARRAY. A 2-D IMAGE DATA STREAM WOULD PROPAGATE IN NEURONLIKE ASYNCHRONOUS PULSE CODED FORM THROUGH THE LAMINAR PROCESSOR. NO MULTIPLEXING, DIGITIZATION OR SERIAL PROCESSING WOULD OCCUR IN THE PREPROCESSING STAGE. HIGH PERFORMANCE IS EXPECTED BECAUSE APPROXIMATELY LINEAR PULSE CODING HAS ALREADY BEEN OBSERVED FOR INPUT CURRENTS RANGING OVER SIX ORDERS OF MAGNITUDE DOWN TO ONE PICOAMPERE WITH NOISE REFERRED TO INPUT OF ABOUT 10 FEMTOAMPERES. EXTREMELYLOW POWER DISIPATION SUGGESTS UTILITY IN SPACE AND IN CONJUNCTION WITH VERY LARGE ARRAYS. MULTISPECTRAL PROCESSING IS POSSIBLE BECAUSE OF COMPATIBILITY WITH THE CRYOGENIC ENVIRONMENT OF HIGH PERFORMANCE INFRARED DETECTORS. RESEARCH INDICATING THE FEASIBILITY OF THE APPROACH WOULD BE CARRIED OUT UNDER PHASE I AND A FULL SCALE PROTOTYPE WOULD BE BUILT, TESTED AND EVALUATED UNDER PHASE II.