A VLSI NEUROCOMPILER FOR MASSIVELY INTERCONNECTED MODELS

MASSIVELY INTERCONNECTED COMPUTERS, COMMONLY CALLED NEUROCOMPUTERS, ARE AT THE HEART OF SIXTH-GENERATION COMPUTING. TO DATE, HOWEVER, ONLY NEUROCOMPUTER SIMULATORS AND EMULATORS ARE AVAILABLE. THIS RESEARCH PROJECT WILL DEVELOP TOOLS AND TECHNIQUES TO TRANSLATE NEUROCOMPUTERS INTO COMPUTATIONALLY EQUIVALENT DIGITAL VLSI CIRCUITS. CONCEPTS FROM SWITCHING CIRCUIT THEORY WILL BE USED TO TRANSLATE INDIVIDUAL NODES OR GROUPS OF NEUROCOMPUTER NODES INTO AN EQUIVALENT DIGITAL CIRCUIT. A STOCHASTIC OPTIMIZATION TECHNIQUE, BASED ON THE GENETIC ALGORITHM, WILL BE DEVELOPED TO TRANSFORM THE DIGITAL LOGIC CIRCUIT SO THAT IT MEETS ANALYST SPECIFIED AREA AND RESPONSE-TIME REQUIREMENTS. THE DEGREE OF FAULT-TOLERANCE REQUIRED BY THE ANALYST WILL BE ADDED INTO THE DESIGN USING TECHNIQUES FROM CODING THEORY. THE TOOL DEVELOPED DURING THIS RESEARCH, CALLED A NEUROCOMPILER, WILL GENERATE VHDL DESCRIPTIONS OF THE RESULTING DESIGNS SO THAT SILICON COMPILERS CAN COMPLETE THE TECHNOLOGY DEPENDENT (E.G., CMOS) ELEMENTS OF THE DESIGN. THE NEUROCOMPILER WILL ALSO INTERFACE WITH CHIP PROGRAMMERS AND PRINTED CIRCUIT BOARD DESIGNERS FOR SMALLER SCALE CHIP PRODUCTION.