Separation of Carrier Lifetime from Interface Recombination Velocity

This Small Business Innovation Research Phase I project will separate minority-carrier lifetime measurements on Silicon-on-Insulator (SOI) wafers. We have already implemented an effective carrier lifetime measurement to characterize SOI samples as thin as 50 nm. this proposal will improve our non-invasive probe of the electrical quality of semiconductor wafers to explicityly and separately characterize the quality of the layer interfaces and the quality of the layer material. This technique can be used to screen wafers of the ascertain total impact of specific process steps, as well as being a routine qualification of some processes. Modern manufactruing technology requires an increasingly detailed statistical summary of the impact of processes on devices. Non-invasive techniques that can probe samples without interfering with a process line operation are crucial in this goal. The present technique extends work performed by other workers for use on bulk silicon wafers. We expect it to prove similarly useful on SOI material. We also expect to apply this technique to other materials, especially wide-band-gap materials such as SiC that cannot be measured by currentyly abailable commercial instruments designed for bulk silicon wafers.