MANUFACTURE OF A VERY HIGH SPEED, RADIATION-RESISTANT, LOW-POWER VERY LARGE SCALE INTEGRATED CIRCUIT TO INTERFACE SILICON MICROSTRIP DETECTORS

THIS PROGRAM'S OBJECTIVE IS TO DEMONSTRATE THE USE OF EXISTING VERY LARGE SCALE INTEGRATED (VLSI) CIRCUIT TECHNOLOGY TO MANUFACTURE A SINGLE-CHIP COMPONENT THAT WILL INTERFACE SILICON MICROSTRIP DETECTORS TO THE SUPERCONDUCTING SUPER COLLIDER'S (SSC'S) CENTRAL PROCESSOR SYSTEM FOR CHARGED PARTICLE DETECTION. THE VLSI COMPONENT WILL CONTAIN 128 PARALLEL CHANNELS, EACH OF WHICH WILL COMPRISE 4-BIT PULSE-HEIGHT DATA ACQUISITION, AN 80-BIT CUSTOM PROCESSOR FOR SIGNIFICANT EVENT DETERMINATION, AND FIBER OPTIC DRIVERS FOR OUTPUT. DATA THROUGH-PUT THROUGH ALL CHANNELS WILL BE CLOCKED SIMULTANEOUSLY AT 62.5 MHZ WITH OVER-ALL POWER DISSIPATION AT LESS THAN 5 MW PER CHANNEL. SAMPLES OF THE VLSI COMPONENT WILL BE PRODUCED USING PROPRIETARY NEW ULTRA HIGH SPEED TECHNOLOGY, VERTICALLY INTEGRATED INJECTION, WHICH IS BEING USED TO DEVELOP SINGLE-CHIP, SUPERCOMPUTER PROCESSORS AND MEMORIES ON SILICON. THIS TECHNOLOGY AIMS AT 9,500 MHZ CLOCK- SPEED AND OFFERS 10 TO 30 TIMES LOWER POWER DISSIPATION (PER GATE)THAN OTHER STATE-OF-THE-ART GAAS OR SI-BASED TECHNOLOGIES. IT IS BASED ON A NEW DEVICE USED TO REPLACE THE CONVENTIONALTRANSISTOR THAT IS THE CORNERSTONE OF ALL OTHER KNOWN VLSI TECHNOLOGIES. ADVANTAGES ARE THE SUPERIOR RADIATION HARDNESS (THERE ARE NO P-N JUNCTIONS TO THE SUBSTRATE), ITS HIGH SPEED AT 2 UM MINIMUM FEATURE SIZE (5 TO 7 PICOSECONDS LOGIC GATE DELAYS WITH 30 MIL OF INTERCONNECT), AND VERY HIGH INTEGRATION DENSITY (100,000 GATES IN 190 MIL(2) AT 2 UM). THE VLSI COMPONENT WILL BE MOUNTED ON A COMMON SUBSTRATE WITH THE MICROSTRIP DETECTOR ITSELF FOR HIGHEST SPEED AND SIGNAL DETECTION EFFICIENCY. THE INTEGRATED CIRCUIT (IC) WILL BE ASSEMBLED AT IOWA STATE UNIVERSITY'S INSTITUTE OF PHYSICAL RESEARCH AND TECHNOLOGY.