Random Access Detector Array for 3-Dimensional Memories

We propose to develop a CMOS based detector array for holographic memories. The detector array has 512 x 512 pixels and is capable of retrieving data from any page oriented optical memory at a rate of 1.28 Gbit/sec. The output bus from the detector array contains 64 channels with each channel operating at up to 20 Mbit/sec. All control and digitizing circuits reside on the same chip. Data on the detector array can be accessed in random. The TTL compatibility of the proposed detector array allows the digital output channels to be interfaced directly to other electronic processors or memories. The power consumption of the proposed device is comparable to a 256kbit RAM chip which is less than 0.1W. The proposed device is applicable to any page-oriented memories such as holographic, two-photon and spectral hole burning based storage systems. In comparison, CCD arrays, which is traditionally used for 3-D memories are bulky, difficult to use, and expensive (for multi-channel device).