FAIL-SAFE FAULT-TOLERANT ELECTRONICS

FUTURE MILITARY AVIONICS SYSTEMS WILL REQUIRE AT LEAST AN ORDER OF MAGNITUDE IMPROVEMENT IN MEAN TIME BETWEEN CRITICAL FAILURES. TO ACHIEVE THIS GOAL INNOVATIVE FAIL-SAFE FAULT-TOLERANT ELECTRONIC SYSTEM DESIGN CONCEPTS WILL BE NEEDED. THE APPROACH PROPOSED BY DAINA WILL BE BASED ON THE USE OF EXTERNAL ENVIRONMENT DATA, BUILT-IN RELIABILITY MODEL, ADAPTIVE STATISTICAL SYSTEM STATE AND PARAMETER ESTIMATORS, SOFTWARE HOOKS, SIGNAL FUSION, AND APPLICATION OF ARTIFICIAL INTELLIGENCE TECHNIQUES. IT IS EXPECTED THAT BY MAXIMIZING THE UTILIZATION OF THE AVAILABLE INFORMATION MORE RELIABLE FAULT DETECTION AND ISOLATION WILL BE ACHIEVED, RELIABILITY IMPROVED, AND FALSE ALARM RATE DECREASED, ALLOWING THE AIRCRAFT TO CONTINUE MISSION EVEN AFTER EXPERIENCING HARDWARE OR SOFTWARE FAILURES OR COMBAT DAMAGE. IMPROVEMENT IN FAULT-TOLERANT SYSTEM DESIGN AIDS WILL BE RECOMMENDED TO SUPPORT RELIABILITY AND SAFETY EVALUATION OF THE PROPOSED DESIGNS. PHASE I OF THIS EFFORT WILL INCLUDE AN ASSESSMENT OF AVIONICS SYSTEM REQUIREMENTS, IDENTIFICATION OF HIGH-PAYOFF HARDWARE AND SOFTWARE TECHNOLOGIES, EVALUATION OF REDUNDANCY AND RECONFIGURATION IMPLEMENTATION, AND DETERMINATION OF COMPUTER-AIDED DESIGN SUPPORT TOOL NEEDS. PHASE II WILL INVOLVE A PROTOTYPE DEVELOPMENT OF THE SELECTED FAIL-SAFE FAULT-TOLERANT ELECTRONICS AND THE SUPPORTING TECHNOLOGY NEEDS.