SBIR Phase I: Software-Based Clock Recovery for Dense Wavelength-Division Multiplexing (DWDM) Applications

This Small Business Innovation Research Phase I project will investigate the feasibility of a novel software-based clock and data recovery (SCDR) solution based on a programmable implementation of all critical components in a phase-lock loop (PLL) based clock and data recovery (CDR). This software-based implementation will allow CDR operation for programmable data rates and data formats. The proposed CDR implementation will be able to process new data formats through software upgrade allowing complete adaptability and upgrade-ability. State-of-the-art high-performance dense wavelength-division multiplexing (DWDM) optical data transmission systems typically use hybrid clock and data recovery assemblies based on passive filter (usually dielectric resonator based) clock recovery techniques to achieve superior system margins. This technology does not allow the CDR circuit to be adaptable to different data formats (NRZ, RZ, duo-binary, etc.), data rates (9.953Gb/s and forward error correction rates), or jitter transfer/tolerance requirements. Competing CDR implementations using phase-locked loop (PLL) techniques often suffer from insufficient jitter transfer and jitter tolerance performance and usually deliver inferior performance in high-end transmission systems. The purely digital SCDR implementation is compatible with today's fine-line CMOS technologies and will lead to programmable CMOS-based precision CDR technology for LH and ULH DWDM applications. In-service eye and Q-factor monitoring capability is available with minimum overhead.