A VLSI DIGITAL TESTER BASED UPON A SINGLE CUSTOM CHIP PER INDIVIDUAL PIN

IN THIS PHASE I, SIX-MONTH FEASIBILITY STUDY WE PROPOSE TO GENERATE A PLAN FOR A SYSTEM ARCHITECTURE FOR A DIGITAL VLSI CHIP TESTER. THE TESTER WILL BE DESIGNED TO INTERFACE TO THE DESIGN WORKSTATION TO ALLOW INTERACTIVE DEBUGGING OF PROTOTYPE CIRCUITS AND SUBSEQUENT DOWN LOADING OF TEST PATTERNS AND EXPECTED RESULTS TO A PRODUCTION VLSI TESTER. THE TESTER WILL BE LOW IN COST BECAUSE IT WILL NOT PERFORM ANALOG TESTING AND BECAUSE EACH INDIVIDUAL PIN OF THE DEVICE UNDER TEST WILL BE DIRECTLY TESTED BY A DEDICATED TESTING INTEGRATED CIRCUIT. THE FUNCTIONAL DESIGN OF THIS TESTING CHIP WILL BE GENERATED, THE CIRCUIT WILL BE COMPLETELY DESIGNED USING PATH PROGRAMMABLE LOGIC, AND IT WILL BE SIMULATED DURING PHASE I. THE CHIP WILL BE FABRICATED AND THE COMPLETE TESTER SYSTEM (HARDWARE AND SOFTWARE) WILL BE COMPLETED IN PHASE II.