Radiation-Hardened High-Speed Synchronous SRAM with Built-in Fault Tolerance

"The objective of this project is to produce complementary-metal-oxide-semiconductor (CMOS) static-random-access memories (SRAMs) which combine very high operational speed, radiation hardness, amenability to emdedded silicon-on-chip (SOC) applications, highpacking density, low power consumption and manufacturability at reasonable costs. The technical approach is based on radiation hardened circuit-modules which are used to create SRAM-circuit organizations for dual, i.e. military and commerical,applications. Novel algebraic multiplicative, synchronous multibank, shuffle and associative repair circuit organizations, and innovative hardened memory cell, self-compensating current sense amplifier, multiple-error detector and corrector and faultmasking component circuits, are to provide short access times and fault-tolerence in radiation environments. In Phase I the feasibility of the novel circuit organizations and component circuits were convincingly demonstrated, in Phase II test-chips andcomplete military SRAMs will be designed, fabricated and evaluated, and in Phase III modified SRAM designs will be commericalized. The outcome of this effort will be elements in future defense systems, satellites, nuclears weapons, power sources,propulsion devices and in other DoD and civilian systems and equipment."