Improved Vertex Focal Plane Arrays for Linear Colliders

The physics of future Linear Colliders (LCs) demand the best possible vertex detector performance, including high-granularity, high-precision, high-efficiency, triggerless operation, and thin cross sections. These requirements generally rule out the use of conventional CCD (charge coupled device) detectors and hybrid complementary metal-oxide semiconductor (CMOS) imagers, which have been used in the past for high energy physics experiments. Monolithic CMOS imagers offer an alternative, but, to date, a CMOS imager meeting the LC requirements has not been demonstrated. This project will develop a robust, low cost, monolithic, silicon-on-insulator CMOS (SOI CMOS) detector that can meet the demanding LC requirements. In Phase I, a commercial, 300mm-capable semiconductor foundry will be used to design, fabricate, and characterize prototype, low-occupancy, fully-depleted, 15-micron thick, small-sized, SOI CMOS detector arrays. Three alternative pixel architectures will be fabricated and tested. In Phase II, fully-functional 22mm x 22mm SOI CMOS vertex detectors will be fabricated, their performance will be evaluated, radiation and particle testing will be conducted, and reliability testing will be performed. Commercial Applications And Other Benefits as described by the Applicant: Highly efficient, high speed, low noise, SOI CMOS vertex detectors should find use in a variety of applications, including commercial and DoD star trackers for celestial reference frames, space surveillance, low light level imaging, electron-microscopy imagers, fluorescence microscopy, DNA sequencing and genomics, soft-xray and EUV imaging, and automobile laser radar (LADAR) cruise control and obstacle avoidance systems