POLYCRYSTALLINE DIAMOND JFETS

THE OBJECTIVE OF THIS PROGRAM IS TO DETERMINE THE FEASIBILITY OF AN ALL DIAMOND JUNCTION FIELD EFFECT TRANSISTOR (JFET). THIS DEVICE IS CONSTRUCTED FROM LARGE GRAIN (5-10 MICRONS), DOPED CVD DIAMOND FILMS AND INCORPORATES GRAIN BOUNDARY PASSIVATION WITHIN THE ACTIVE CHANNEL REGION. CURRENT FLOW IN THE JFET IS CONFINED TO THE SINGLE CRYSTAL REGIONS IN THE POLYCRYSTALLINE FILM ELIMINATING THE IMPACT OF GRAIN BOUNDARY SCATTERING ON DEVICE SPEED. THE DEVICE IS CONSTRUCTED WITH A THICK (2-10 MICRON) SUBSTRATE LAYER OF COMPENSATED CVD DIAMOND, A BORON DOPED CHANNEL AND A NITROGEN DOPED GATE. A DIAMOND JFET WILL HAVE A BUILT IN VOLTAGE OF APPROXIMATELY 4.0 VOLTS AND IS WELL MATCHED TO THE BANDGAP OF DIAMOND SO AS TO ALLOW VERY HIGH TEMPERATURE OPERATION WHILE ALSO OPERATING AT ROOM TEMPERATURE. IN THIS PROPOSED DEVICE CONFIGURATION THE N+ DIAMOND GATE ALSO FUNCTIONS AS A GATE INSULATOR ALLOWING LARGE VOLTAGE SWINGS OF EITHER POLARITY WITHOUT CONDUCTING SIGNIFICANT CURRENT. THE NITROGEN DOPED GATE LAYER FUNCTIONS AS BOTH GRAIN BOUNDARY AND DEVICE PASSIVATION LAYER.