MULTIPLE ION IMPLANTATION OF BURIED LAYERS FOR SILICON-ON-INSULATOR

FABRICATING SILICON-ON-INSULATOR (SOI) SUBSTRATE IS A SUBJECT OF KEEN INTEREST BECAUSE OF THE WIDE VARIETY OF MAJOR ELECTRICAL BENEFITS THATCAN BE OBTAINED FOR INTEGRATED CIRCUITS. THE MOST PROMISING TECHNOLOGY IS ION IMPLANTATION OF BURIED LAYERS BECAUSE OF PROCESS CONTROLLABILITY, MILD DEFECTS, AND LARGE AREA UNIFORMITY. COMPLEX DEVICE FABRICATION HAS BEEN SUCCESSFULLY DEMONSTRATED. THE IMPLANTATION TECHNIQUE LENDS ITSELF TO A VARIETY OF NOVEL PROCESS MODIFICATIONS TO ENHANCE THE PERFORMANCE OF THE BASIC SOI MATERIAL. METHODS ARE BEING INVESTIGATED FOR CREATING MUCH HIGHER VOLTAGE ISOLATION THAN NORMALLY AVAILABLE AND SIGNIFICANTLY DECREASED PARASITIC CAPACITANCE. A UNIQUE MULTIPLE ION IMPLANT PROCESS IS BEINGUSED TO FABRICATE THE MATERIAL. THE SILICON-ON-INSULATOR SUBSTRATES BEING FABRICATED ARE ESPECIALLY USEFUL FOR MIXING VERY HIGH VOLTAGE CIRCUIT ELEMENTS WITH CONTROL STRUCTURES. THIS IS IMPORTANT FOR RADIATION-HARD POWER CONTROL DEVICES. THE DECREASED PARASITC CAPACITANCE GEOMETRY IS IMPORTANT FOR INCREASING DEVICE SPEED, DECREASING GATE THRESHOLD SENSITIVITY TO SUBSTRATE BIAS, AND CORRECTING THE KINK FREQUENTLY OBSERVED IN THE CHARACTERISTIC DEVICE CURVES.