A Monolithic Smart Switched Photodiode Array for 1.0-1.7 um

We propose to design, fabricate and demonstrate 1x32 and 32x32 element monolithic arrays of "smart-switched" InGaAs photodetectors. In Phase I, we will design and build the basic monolithic InGaAs JFET/detector cell in the form of a simple adder circuit. We will indium "bump-bond" the pixel onto a linear silicon multiplexer to demonstrte feasibility of our concept. In Phase II, we will optimize the device structure and make 1x32 one-dimensional and 32x32 element two-didmensional arryas of the monolithic JFET/detector pixels and complete our design of the silicon thresholding and decision circuits. We will fabricate these CMOS circuits via the MOSIS process, bump-bond them to the 32x32 element array and package it in a hermetically sealed package, suitable for either fiber optic or focal plane input. Prof. S.R. Forrest (Princeton University) will consult on the project. A Phase I option is included.