SCHEDULING TECHNOLOGY FOR SEMICONDUCTOR FABRICATION

MINIATURIZATION OF ELECTRONIC COMPONENTS INTO INTEGRATED CIRCUITS (SEMICONDUCTOR DEVICES) HAS DRAMATICALLY AFFECTED OUR LIVES. NO WHERE IS THIS MORE APPARENT THAN THE LARGE DEPENDENCY AMERICAN MANUFACTURING HAS ON SEMICONDUCTOR DESIGN AND FABRICATION. THE PRODUCTION OF AN INTEGRATED CIRCUIT REQUIRES A FOUR STAGE PROCESS: 1) WAFER FABRICATION; 2) WAFER PROBE; 3) ASSEMBLY (PACKAGING); AND 4) FINAL TEST. BECAUSE OF THE HIGH CAPITAL COSTS AND FAIRLY LOW VARIABLE RATE PRODUCTION COSTS, MANUFACTURERS OF SEMICONDUCTORS TRY TO MAINTAIN HIGH UTILIZATION OF THE WAFER FABRICATION EQUIPMENT. THE PROPOSED RESEARCH FOCUSES ON THE TASK OF EFFECTIVELY GENERATING SCHEDULES WHICH IMPROVE PERFORMANCE OF THE PRODUCTION SYSTEM. WITH A SMALL NUMBER OF BOTTLENECK PROCESSES DOMINATING THE SCHEDULE, IT IS REASONABLE TO EXPECT THAT CONCEPTS SUCH AS AGGREGATIONAND DECOMPOSITION CAN BE APPLIED TO REDUCE THE ORIGINAL PROBLEM TO ONE WHICH ESSENTIALLY INVOLVES ONLY THE BOTTLENECK PROCESSES. THEN, GIVEN A SOLUTION TO THE SIMPLERPROBLEM, TECHNIQUES OF DISAGGREGATION CAN BE APPLIED TO "EXPLODE" THE SOLUTION INTO THE FULL SCHEDULE.