Multiprocessor & ASIC Standard Interconnect for Space Systems

The development of a radiation hardened crossbar switch, which embodies theinterconnect protocol developed in Phase I, is proposed. The end productwill be an eight port crossbar switch ASIC, whose total bisection data rateis 6 Gbps. The first step is to validate the interconnect standard and VHDLdescription of the standard, which was developed in Phase I. Thisvalidation will be done with a custom FPGA based hardware emulator on a VMEtest chassis. Concurrently, an LVDS driver and receiver macrocell will bedesigned for the targeted semiconductor process. LVDS will be used as thebasis for the physical layer interconnects. A test chip will bemanufactured which incorporates these LVDS macrocells. The test chip willthus be used to validate the performance of the physical layer. Uponsuccessfully completing the test chip and fully emulating the VHDL codebehind the protocol, an ASIC will be designed. The ASIC will bemanufactured on a semiconductor process that has inherent total doseimmunity. After manufacturing, the rad-hard crossbar switch will bereinserted into the VME test setup and its performance will be evaluated andcharacterized.