SBIR/STTR Research Award

Advanced Digital Array Radar (DAR) Adaptive Beamformer and Pulse Compression Processor

Award identifier 9d08c1714c1be7eb52983c6c76c07a8a8eeada817dc558a6703b00d9ff64eb8fAwarding agency Department of Defense · Navy

Award amount

$69,515

Program and phase

SBIR · Phase I

Award year

2003

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
SYSTEMS SOFTWARE INTERNATIONAL
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

Adaptive Digital Array Radars (DARs) promise significant sensor performance breakthroughs when antenna arrays become sufficiently large to achieve useful gain and directivity. Recent electronics technology advancements have progressed to the point thatadaptive DAR sensors will soon support operational requirements for many important US Navy applications.A Reconfigurable DAR Processor (RDP) addresses several DAR-related needs: a test bed for pulse compression (PC) and adaptive beamforming (ABF) algorithm development; field testing of digital array antennas; and a complete space-time adaptive processor(STAP) for first generation adaptive DARs. The proposed design employs a large network of FPGA-based DSP nodes distributed over several line cards interconnected by a full serial mesh backplane. Notional designs at the chassis level, line card level andDSP node level are presented. The design uses two levels of firmwave reconfiguration: system maintenance and functional upgrades; and rapid reconfigurations allowing on-the-fly STAP re-functioning to follow radar mode changes. An efficient firmwaredevelopment methodology facilitating DSP element re-use is presented.Phase 1 activities: review of PC, ABF and other DAR-related STAP functions; analysis of a calibration concept for non-adaptive beamforming that simultaneously generates accurate ABF steering vectors; RDP requirements definition and system design;development of a DSP firmware design library. The Reconfigurable DAR Processor (RDP) provides a flexible platform that can host a wide range of systems that process high-speed input data streams, generate high-speed output data streams, perform large-scale computational tasks, or any combinationthereof. Our plan is to use the RDP on several future R&D efforts primarily for DoD customers, and secondarily for targeted commercial and other-government opportunities (such as telecommunications) arising from our commercialization strategy. One DoDcustomer has been identified that is interested in providing Phase II Fast Track matching funds.

Technology keywords

Not reported

Agency intelligence

Department of Defense

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