Suppression of Step Bunching During High Temperature Anneals of SiC

Many approaches to realizing the full potential of the Power Electronic Building Block rely upon the remarkable electronic properties of SiC. Almost all of these involve high temperature treatment of SiC, whether for growth, oxidation, or implant activation anneal. Unfortunately, under high temperature processing this material has demonstrated the occurrence of step bunching. This surface/interface roughness of course leads to increased carrier scattering, thereby degrading device performance. In general, the technique of reflectance anisotropy spectroscopy is sensitive to reduced symmetry at the surface, including steps; increased signal at some critical points has been found to be associated with step-like surface structures. However, the critical points for SiC occur for hvo 6eV, which is inaccessible to normal spectrometers. We therefore propose to develop a new means to characterize this surface/interface. This tool, Far Ultraviolet Reflectance Anisotropy Spectroscopy, offers promise of improved characterization of SiC surfaces, as well as those of other wide bandgap semiconductors such as GaN. This technique permits us to characterize step bunching as it occurs, as it is a non-contact optical technique permitting remote access.