A MODULAR VLSI ARCHITECTURE FOR COINCIDENCE DETECTION IN POSITRON EMISSION TOMOGRAPHY

THIS STUDY WILL INVESTIGATE THE FEASIBILITY OF IMPLEMENTING A NEW ARCHITECTURE FOR PART OF THE PROCESSING REQUIRED TO RECONSTRUCT IMAGES FOR POSITRON EMISSION TOMOGRAPHY. IMPLEMENTING THIS NEW ARCHITECTURE FOR COINCIDENCE DETECTIONIN A VERY LARGE SCALE INTEGRATED (VLSI) CIRCUIT SHOULD NOT ONLY REDUCE THE SIZE AND COST OF THE CIRCUITRY, BUT SHOULD ALSO REDUCE THE LENGTH REQUIREMENTS OF AN EXPENSIVE HIGH SPEED CABLE. THE ARCHITECTURE IS PRACTICAL ONLY IN VLSI SINCE IT REQUIRES A LARGE NUMBER OF INTERNAL CONNECTIONS. HOWEVER, THE SILICON AREA NEEDED FOR MAKING THESE CONNECTIONS WILL BE MINIMIZED BY EMPLOYING NEAREST-NEIGHBOR COMMUNICATION WITHIN THE ARRAY OF MODULES. FURTHERMORE, THE ARCHITECTURE'S DESIGN COMPLEXITY WILL BE KEPT MANAGEABLE BY REPLICATING A SINGLE MODULE 56 TIMES WITHIN THE ARRAY. PHASE I WILL CONSIST OF MAPPING THE DESIRED FUNCTIONS INTO A SEMICUSTOM VLSI CIRCUIT AND COMPARING THIS IMPLEMENTATION WITH AN EXISTING DISCRETE IMPLEMENTATION. THE FEASIBILITY OF PROCEEDING ON TO DESIGN AND MANUFACTURE OF THE VLSI IMPLEMENTATION THEN WILL BE EVALUATED.