SBIR/STTR Research Award
KA-BAND, HIGH EFFICIENCY POWER MMIC
Award amount
$494,358Program and phase
SBIR · Phase IIAward year
1992Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- Schellenberg Assoc
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
THIS PROJECT WILL DEVELOP A 500 MW MMIC OPERATING AT 35 GHZ WITH A CHIP-SUPPLY VOLTAGE OF 28 VOLTS AND A POWER-ADDED EFFICIENCY OF MORE THAN 40 PERCENT. THESE RESULTS WILL BE ACHIEVED BY EMPLOYING TWO CIRCUIT INNOVATIONS: A SERIES-CELLCONFIGURATION AND AN ON-CHIP, HIGH-EFFICIENCY COMBINER. THEUNIQUE SERIES-CELL CONFIGURATION RESULTS IN A HIGH-CHIP-BIASVOLTAGE (28 VOLTS) BECAUSE THE FET CELLS ARE BIASED IN SERIES INSTEAD OF IN PARALLEL, AS WITH CONVENTIONAL ICS. THIS GREATLY INCREASES THE EFFICIENCY OF THE SYSTEM EMPLOYING THE CHIPS AND EVEN PERMITS THE IC TO OPERATE DIRECTLY FROM THE SPACECRAFT BUS, THEREBY ELIMINATING THE LOSSES IN THE POWER-CONDITIONING CIRCUITRY (DC-TO-DC CONVERTER AND REGULATOR). FURTHER, THE HIGH CHIP EFFICIENCYIS ACHIEVED BY EMPLOYING AN ON-CHIP, LOW-LOSS, CELL-COMBINING CIRCUIT THAT SIMULTANEOUSLY COMBINES AND MATCHES THE FET CELLS WITH A COMGINING EFFICIENCY OF 95 PERCENT. THIS WORK WILL HAVE A MAJOR IMPACT ON THE WAY THAT HIGH-EFFICIENCY POWER MMICS ARE DESIGNED IN THE FUTURE. IN PARTICULAR, THIS WORK COULD BE EXTREMELY IMPORTANT FOR SATELLITE- AND SPACECRAFT-BASED COMMUNICATION LINKS, FOR WHICH PRIME POWER CONSUMPTION IS A MAJOR CONCERN. THIS PROJECT WILL DEVELOP A 500 MW MMIC OPERATING AT 35 GHZ WITH A CHIP-SUPPLY VOLTAGE OF 28 VOLTS AND A POWER-ADDED EFFICIENCY OF MORE THAN 40 PERCENT. THESE RESULTS WILL BE ACHIEVED BY EMPLOYING TWO CIRCUIT INNOVATIONS: A SERIES-CELLCONFIGURATION AND AN ON-CHIP, HIGH-EFFICIENCY COMBINER. THEUNIQUE SERIES-CELL CONFIGURATION RESULTS IN A HIGH-CHIP-BIASVOLTAGE (28 VOLTS) BECAUSE THE FET CELLS ARE BIASED IN SERIES INSTEAD OF IN PARALLEL, AS WITH CONVENTIONAL ICS. THIS GREATLY INCREASES THE EFFICIENCY OF THE SYSTEM EMPLOYING THE CHIPS AND EVEN PERMITS THE IC TO OPERATE DIRECTLY FROM THE SPACECRAFT BUS, THEREBY ELIMINATING THE LOSSES IN THE POWER-CONDITIONING CIRCUITRY (DC-TO-DC CONVERTER AND REGULATOR). FURTHER, THE HIGH CHIP EFFICIENCYIS ACHIEVED BY EMPLOYING AN ON-CHIP, LOW-LOSS, CELL-COMBINING CIRCUIT THAT SIMULTANEOUSLY COMBINES AND MATCHES THE FET CELLS WITH A COMGINING EFFICIENCY OF 95 PERCENT. THIS WORK WILL HAVE A MAJOR IMPACT ON THE WAY THAT HIGH-EFFICIENCY POWER MMICS ARE DESIGNED IN THE FUTURE. IN PARTICULAR, THIS WORK COULD BE EXTREMELY IMPORTANT FOR SATELLITE- AND SPACECRAFT-BASED COMMUNICATION LINKS, FOR WHICH PRIME POWER CONSUMPTION IS A MAJOR CONCERN.
Technology keywords
Not reported