BIST FOR OTS AND ASIC VLSI DESIGNS WITH VHDL

THE EMERGENCE OF VLSI TECHNOLOGY HAS INCREASED THE COMPLEXITY OF INTEGRATED CIRCUIT DEVICES, IN TERMS OF TRANSISTORS PER DEVICE, AT A RATE MULTIPLYING BY 100 EVERY 10 YEARS. NEW TECHNOLOGIES, SUCH AS SURFACE MOUNT, REQUIRE SPECIAL TECHNIQUES TO MAKE THE BOARDS TESTABLE. THE GOAL OF THIS RESEARCH AND DEVELOPMENT PROJECT IS TO REVIEW RELATED RESEARCH AND DEVISE VARIOUS WAYS TO SEMIAUTOMATICALLY ADD BUILT-IN-SELF-TEST (BIST) TO EXISTING DESIGNS -AT THE SYSTEM, BOARD AND A MIXTURE OF CUSTOMIZABLE AND NON-CUSTOMIZABLE DEVICES. CONSIDERATION WILL BE GIVEN TO USING MACHINE READABLE DESCRIPTIONS (NET LISTS AND BEHAVIORAL MODELS) FOR INPUT, AND WHERE POSSIBLE, AUTOMATICALLY ADDING BIST TO OFF-THE-SHELF AND ASIC VLSI DESIGNS. INDUSTRY STANDARD VHSIC HARDWARE DESCRIPTION LANGUAGE (VHDL) AS WILL BE THE PREFERRED STANDARD FOR THE SEMIAUTOMATIC PROCESS. DURING PHASE II, GENERIC BOUNDARY SCAN TEST CIRCUITS OR OTHER TECHNIQUES AS A SUBSET OF THOSE CONSIDERED FOR PHASE I WILL BE CONSTRUCTED AND TESTED WITH SAMPLE BEHAVIORAL AND STRUCTURAL VHDL MODELS. COMMERCIAL SUPPLIERS OF VHDL DESIGN AUTOMATION TOOLS WILL BE INVITED TO PARTICIPATE IN FURTHER COMMERCIAL PRODUCT DEVELOPMENT. PROOF OF CONCEPT WILL ALSO BE ATTEMPTED DURING PHASE I.