VHDL Behavioral Synthesis Tool for Low Power Based on FRITS

Low power has been recently elevated to one of the most critical issues in circuit design, affecting circuit reliability, battery life, and heat sinking. In spite of this demand, surprisingly little support from CAD vendors exists for automated low power circuit design. Alternative System Concepts (ASC) and Princeton University propose to design and develop a much needed power optimizing design automation tool incorporating recent research advances in the area of high-level synthesis for low power. The proposed development tightly couples advanced research at Princeton and innovative VHDL-based CAD tools developed by ASC. The new tool will implement VHDL behavioral synthesis for low power, transforming a behavioral VHDL description into a structural VHDL description, optimized for power dissipation. Power minimization will be achieved by simultaneously applying: 1) voltage scaling for fixed throughput; 2) minimization of switching activity in the circuit; 3) reduction of capacitive loads through minimization of module count and interconnect. Combining low power, area, and performance as co-objectives in the synthesis process will ensure globally optimal designs. Existing and newly developed methods for transformation, scheduling, and allocation will be integrated into ASC's FRITS object-oriented VHDL framework.