BX1750-A ENHANCEMENTS FOR LOW-POWER DSP

THIS PHASE I PROGRAM IS DESIGNED TO ENHANCE THE PERFORMANCE OF AN EXISTING MIL-STD-1750A PROCESSOR, THE BX1750A, MANUFACTURED BY THE MICROELECTRONICS DIVISION OF ALLIED SIGNAL. THE METHODOLOGY PROPOSED, TO INCORPORATE THE ENHANCEMENTS FOR DIGITAL SIGNAL PROCESSING (DSP), MAKES EXTENSIVE USE OF THE BUILT-IN-FUNCTION (BIF), AN OPTIONAL FEATURE OF THE 1750A STANDARD, WHEREBY CUSTOMIZED INSTRUCTIONS CAN BE INCORPORATED INTO ON-CHIP MICROCODE ROM AND CALLED BY A SPECIAL OPCODE PLUS EXTENSION. MAJOR TASKS IN PHASE I WILL BE 1. SELECTION OF MAJOR SIGNAL PROCESSING FUNCTIONS TO BE IMPLEMENTED E.G. TRIG FUNCTIONS, FAST FOURIER TRANSFORM, DIGITAL FILTERS, ETC. 2. EVALUATION OF PERFORMANCE OF MICROCODED DSP FUNCTIONS VS. STRAIGHT SOFTWARE SUB-ROUTINE VERSIONS. 3. ADDITION OF SPECIAL HARDWARE SUPPORT FUNCTIONS SUCH AS SINGLE CYCLE MULTIPLY ACCUMULATE, ZERO OVERHEAD LOOPS, ETC. 4. RECOMMENDATIONS FOR PHASE II IMPLEMENTATION OF ENHANCED 1750A CHIP FOR DSP.