A HIGH-SPEED, FAULT-TOLERANT, MIL-STD-1750A MICROPROCESSOR FOR SPACE APPLICATIONS

ADVANCED SPACECRAFT, SPACE PLATFORMS, AND TRANSPORTATION VEHICLES WILL REQUIRE SEVERAL ORDER-OF-MAGNITUDE IMPROVEMENTS IN THE OPERATIONAL CAPABILITY AND RELIABILITY OF THE GUIDANCE, NAVIGATION, AND CONTROL (GN AND C) SYSTEMS. TO SATISFY THESE REQUIREMENTS, SIGNIFICANT IMPROVEMENTS IN THE THROUGHPUT AND FAULT TOLERANCE OF THE GN AND C COMPUTERS WILL HAVE TO BE REALIZED. THE MAIN OBJECTIVE OF THIS PROPOSAL (PHASES I AND II) IS TO RESEARCH, DEVELOP, CONSTRUCT, AND EVALUATE A LABORATORY PROTOTYPE OF A NOVEL, SINGLE-CHIP, FAULT-TOLERANT, RADIATION-HARD CMOS, MIL-STD-1750A MICROPROCESSOR OPERATING SIGNIFICANTLY FASTER THAN EXISTING MICROPROCESSORS. THE SPECIFIC OBJECTIVE FOR PHASE I IS A FEASIBILITY STUDY OF A NOVEL ARITHMETIC UNIT OF THE MICROPROCESSOR. THE APPROACH PROPOSED FOR INCREASING THE SPEED IS AN INNOVATIVE MULTI-PORT GENERAL PURPOSE REGISTER ARRAY AND TWO SEPARATE ADDERS, ONE FOR THE MANTISSA AND ONE FOR THE EXPONENT OF THE FLOATING-POINT OPERATION. FAULT TOLERANCE OF THE REGISTER ARRAY WILL BE ACHIEVED BY AN ERROR DETECTION AND CORRECTION UNIT BASED ON A MODIFIED HAMMING CODE. THE COMBINATIONAL LOGIC OF THE ADDERS EMPLOYS "FINE-GRAIN" FAULT TOLERANCE. AN INNOVATIVE DIFFERENTIAL CMOS LOGIC CIRCUIT IS USED TO PERFORM DOUBLE-RAIL LOGIC OPERATIONS FOR EFFICIENT FAULT DETECTION. FAULT CORRECTION IS ACHIEVED BY DUPLICATING THE DOUBLE-RAIL ADDERS. THIS COMBINATION IS EXPECTED TO RESULT IN A FAULT-TOLERANT CHIP WHICH IS SIGNIFICANTLY MORE COST-EFFECTIVE THAN PRESENTLY KNOWN FAULT-TOLERANT APPROACHES. THE FAULT TOLERANCE EFFECTIVENESS WILL BE MEASURED AND DEMONSTRATED BY FAULT SIMULATION.