DESIGN OF "SMART" PHASED ARRAYS UTILIZING MASSIVELY PARALLELCOMPUTER ARCHITICTURES

RESEARCH CONDUCTED AT MASSACHUSETTS TECHNOLOGICAL LABORATORY(MTL) HAS DEMONSTRATED SIGNIFICANT GAINS IN EXECUTION SPEED IN PHASED ARRAY ALGORITHMS FOR NULL-STEERING AND ADAPTIVE NULLING BY IMPLEMENTATION IN THE FINE-GRAINED ("DATA LEVEL")PARALLEL COMPUTATIONAL ARCHITECTURE OF THE CONNECTION MACHINE. SUCH WORK SUGGESTS THAT SIGNIFICANT GAINS IN PHASED ARRAY PERFORMANCE MAY BE OBTAINED BY THE DEVELOPMENT OF A "SMART" PHASED ARRAY, WHERE COMPUTATIONAL ELEMENTS ARE DISPERSED AMONG THE PHASED ARRAY ELEMENTS AND AN APPROPRIATENETWORK OF INTERCONNECTIONS FOR TRANSFER OF INFORMATION BETWEEN PROCESSORS IS PROVIDED. SUCH A "SMART" PHASED ARRAYHAS THE POTENTIAL FOR SUBSTANTIALLY REDUCE HIGH DATA-RATE, LARGE BANDWIDTH COMMUNICATION WITH A CENTRAL COMPUTER, AND RAPID (MICROSECOND TIME SCALE) NULLING. ADDITIONAL CAPABILITIES FOR THE REAL-TIME MONITORING OF ARRAY PERFORMANCE AND LIMITED AUTOMATIC FAILURE COMPENSATION ("SELF-HEALING") ALSO APPEAR PROMISING. THE CONNECTION MACHINE ARCHITECTURE IS HIGHLY SUITABLE FOR THE DEVELOPMENT OF ALGORITHMIC TOOLS AND SIMULATIONS FOR THE STUDY OF "SMART" PHASED ARRAYS. A PROGRAM OF RESEARCH TO DEMONSTRATETHE FEASIBILITY OF "SMART" PHASED ARRAYS BY SIMULATIONS ON THE CONNECTION MACHINE AND FOR THE STUDY OF THEIR PROPERTIESIS OUTLINED.